This invention relates to microelectronic devices and fabrication methods therefor, and more particularly to structures and methods of forming electrical and mechanical connections for a microelectronic substrate, and the connections so formed.
Solder bump technology is widely used for electrical and mechanical interconnection of microelectronic substrates. For example, an integrated circuit chip may be connected to a circuit board or other next level packaging substrate using solder bumps. This connection technology also is referred to as xe2x80x9cControlled Collapse Chip Connectionxe2x80x94C4xe2x80x9d or xe2x80x9cflip-chipxe2x80x9d technology, and will be referred to herein as xe2x80x9csolder bumpsxe2x80x9d.
In solder bump technology, an xe2x80x9cUnderBump Metallurgyxe2x80x9d (UBM) may be formed on a microelectronic substrate having contact pads thereon, for example by evaporation and/or sputtering. A continuous underbump metallurgy generally is provided on the pads and on the substrate between the pads, in order to allow current flow during subsequent solder plating.
In order to define the sites for solder bump formation over the contact pads, a mask is formed, for example by forming a thick layer of photoresist on the underbump metallurgy and patterning the photoresist to expose the underbump metallurgy over the contact pads. Solder pads then may be formed on the exposed areas of the underbump metallurgy, over the contact pads, by electroplating. The plated solder accumulates in the cavities of the photoresist, over the contact pads. The underbump metallurgy between the plated solder then may be etched, using the solder as an etch mask, to break the electrical connection between the solder bumps. The plated solder then may be reflowed to form solder bumps. During reflow, the solder bump also may alloy with the underbump metallurgy, to form an intermetallic. Solder bump fabrication methods and structures are described in U.S. Pat. No. 5,162,257 to Yung; U.S. Pat. No. 5,293,006 to Yung; U.S. Pat. No. 5,447,264 to Koopman et al.; U.S. Pat. No. 5,767,010 to Mis et al.; U.S. Pat. No. 5,793,116 to Rinne et al.; U.S. Pat. No. 5,892,179 to Rinne et al.; U.S. Pat. No. 5,902,686 to Mis; and U.S. Pat. No. 5,963,793 to Rinne et al., and need not be described further herein.
As microelectronic technology continues to advance, it may become increasingly desirable to use solder bump technology in an increasing variety of microelectronic devices. Conventional solder bumps use alloys of lead (Pb)-tin (Sn) solder. In these solder bumps, it may be desirable to maintain a high lead content to allow a high degree of flexibility in the solder bump, which can thereby absorb mechanical stresses that may be caused by thermal expansion coefficient mismatches between the substrates that are connected by the solder bumps. Unfortunately, as the lead content of lead-tin solder increases above or below 37% from eutectic lead-tin solder (63 Sn-37 Pb), the melting point of the solder bump generally increases. This increased melting point may require higher temperatures for solder reflow and/or joining. These higher temperatures may damage microelectronic devices in a microelectronic substrate. Moreover, it may be more difficult to form a strong connection between the solder bump and the underbump metallurgy as the lead content continues to increase.
Attempts to provide high performance solder bump connections are described in U.S. Pat. No. 4,673,772 to Satoh et al.; U.S. Pat. Nos. 5,130,779 and 5,251,806 to Agarwala et al.; U.S. Pat. No. 5,542,174 to Chiu; U.S. Pat. Nos. 5,553,769, 5,859,470 and 5,920,125 to Ellerson et al.; U.S. Pat. No. 5,470,787 to Greer; and in a publication entitled An Extended Eutectic Solder Bump for FCOB to Greer, 1996 Electronic Components and Technology Conference, pp. 546-551. However, notwithstanding these and other attempts, there continues to be a need for solder bumps and fabrication methods that can maintain a high lead content, can reflow at relatively low temperatures and/or can alloy effectively with an underbump metallurgy.
The present invention can provide trilayer/bilayer solder bump fabrication methods by plating a first solder layer on an underbump metallurgy, plating a second solder layer having higher melting point than the first solder layer on the first solder layer and plating a third solder layer having lower melting point than the second solder layer on the second solder layer. The structure then is heated to below the melting point of the second solder layer but above the melting point of the first solder layer and the third solder layer, to alloy at least some of the first solder layer with at least some of the underbump metallurgy and to round the third solder layer. Accordingly, a trilayer solder bump may be fabricated wherein the first and third solder layers melt at lower temperatures than the second solder layer, to thereby round the outer surface of the solder bump and to alloy the base of the solder bump to the underbump metallurgy, while allowing the structure of the intermediate layer to be preserved.
Solder bump fabrication as described above may be particularly useful with lead-tin solder wherein the first solder layer comprises eutectic lead-tin solder, the second solder layer comprises lead-tin solder having higher lead content than eutectic lead-tin solder and the third solder layer comprises eutectic lead-tin solder. In these embodiments, the first and third eutectic lead-tin solder layers can provide a lowest melting point for rounding the top and alloying the base of the solder bump. However, the high lead content of the intermediate (second) solder layer may be preserved to provide flexibility for the bump. Moreover, since the first, second and third solder layers are plated, the columnar plated structure within the intermediate solder layer may be preserved, to thereby allow further increases in flexibility. Thus, the second solder layer may be maintained in its xe2x80x9cas platedxe2x80x9d condition.
Embodiments of the invention may be used with underbump metallurgy systems that include an outer layer of copper. In these embodiments, heating may be performed to alloy sufficient tin from the first solder layer with at least some of the outer layer comprising copper, such that the first solder layer is converted to a fourth solder layer having the same lead content as the second solder layer. This can create a bilayer solder bump wherein the second and fourth solder layers have the same lead content, after reflow, and a eutectic third (outer) rounded layer caps the second solder layer. In yet other embodiments, heating is performed to alloy at least some tin from the first solder layer with at least some of the copper outer layer of the underbump metallurgy, such that the first solder layer is converted to a fourth solder layer having higher lead content than eutectic lead-tin solder, but not having the same lead content as the second solder layer. Accordingly, these embodiments may provide trilayer reflowed solder bumps.
In yet other embodiments, the thickness and/or composition of the copper outer layer and/or of the first solder layer may be selected so that upon heating, sufficient tin from the first solder layer is alloyed with all of the copper in the outer underbump metallurgy layer, such that the first solder layer is converted to a fourth solder layer having same lead content as the second solder layer. Bilayer solder bumps thereby may be provided. In yet other embodiments, the thickness and/or composition of the first solder layer and/or of the outer layer of the underbump metallurgy maybe selected to alloy some tin from the first solder layer with all of the copper in the outer layer, such that all of the outer layer is converted to copper-tin alloy and the first solder layer is converted to a fourth solder layer having higher lead content than eutectic lead-tin solder, but not the same lead content as the second solder layer.
Other embodiments of the present invention may be used with underbump metallurgy systems having a nickel outer layer. As was described above in connection with a copper outer underbump metallurgy layer, the thickness and/or composition of the nickel underbump metallurgy layer and/or of the first solder layer may be controlled to alloy some or all of the nickel and/or convert the first solder layer to higher lead-tin content than eutectic lead-tin solder or the same lead content as the second solder layer.
In yet other embodiments of the invention, the first solder layer comprises about 3000 xc3x85 of eutectic lead-tin solder, the second solder layer preferably comprises about 40 microns of solder having higher lead content than eutectic lead-tin solder, and the third solder layer preferably comprises at least about 10 microns of eutectic lead-tin solder. In order to convert all of the underbump metallurgy outer copper layer to copper-tin alloy, about 5000 xc3x85 of copper may be provided. However, other thicknesses and compositions may be provided according to embodiments of the present invention.
Embodiments of solder bump structures according to the present invention include an underbump metallurgy, a first plated solder layer on the underbump metallurgy, a second plated solder layer on the first solder layer having higher melting point than the first solder layer, and a third plated solder layer on the second solder layer having lower melting point than the second solder layer. In other embodiments, the first plated solder layer and the third plated solder both comprise eutectic lead-tin solder, whereas the second plated solder layer comprises lead-tin solder having higher lead content than eutectic lead-tin solder. The underbump metallurgy preferably includes an outer layer comprising copper or nickel. In yet other embodiments, the second plated solder layer may be wider than the first plated solder layer and the third plated solder layer may be wider than the second plated solder layer. In still other embodiments, the first, second and third plated solder layers each include a plurality of columnar grains that extend across the thickness thereof. Embodiments of solder bump structures of this paragraph may form intermediate structures prior to reflow.
In other embodiments, the first solder layer comprises about 3000 xc3x85 of eutectic lead-tin solder, the underbump metallurgy includes an outer layer of copper of about 5000 xc3x85 in thickness, the second solder layer is about 40 microns in thickness, and the third solder layer is at least about 10 microns in thickness. In other embodiments, the third solder layer comprises lead-tin solder having higher lead content than eutectic lead-tin solder, but lower lead content than the second solder layer. Embodiments of this paragraph also may form intermediate structures prior to reflow.
Other embodiments of solder bump structures according to the present invention include an intermetallic layer comprising an alloy of tin and material other than lead, an intermediate solder layer on the intermetallic layer, and an outer solder layer on the intermediate solder layer having lower melting point than the intermediate solder layer. The intermediate solder layer preferably comprises lead-tin solder having higher lead content than eutectic lead-tin solder, and the outer solder layer preferably comprises eutectic lead-tin solder. The intermetallic layer may comprise an alloy of tin and copper, or an alloy of tin and nickel. In these embodiments, the outer solder layer may be wider than the intermetallic layer. Embodiments of this paragraph may form final solder bump structures after reflow.
In other embodiments, the intermediate solder layer may be about 40 microns in thickness, and the outer solder layer may be at least about 10 microns in thickness. The intermediate solder layer preferably includes columnar grains that extend across the thickness thereof, and the outer solder layer preferably includes a rounded outer surface. Embodiments of this paragraph also may form final solder bump structures after reflow.
Other embodiments of solder bump structures according to the present invention include an underbump metallurgy, a rounded solder bump cap and a solder bump body between the underbump metallurgy and the rounded solder bump cap. The solder bump is wider adjacent the rounded solder bump cap than adjacent the underbump metallurgy. In other embodiments, the solder bump body increases in width from adjacent the underbump metallurgy to adjacent the rounded solder bump cap. In yet other embodiments, the solder bump body continuously increases in width from adjacent the underbump metallurgy to adjacent the rounded solder bump cap. These increased width solder bumps may provide high density connections to underbump metallurgy and large surface area outer connections to other microelectronic substrates.
Accordingly, solder bumps and fabrication methods may be fabricated that can maintain high lead content, low temperature reflow, effective alloying with an underbump metallurgy layer and/or as plated columnar grain structures.